A non-volatile memory device does not lose information stored in its memory cells, even when its power is interrupted. This characteristic makes the non-volatile memory device be widely adopted in, e.g., computers, digital cameras, and mobile phones. A flash memory device is one of typical non-volatile memory devices.
The flash memory device is a variation of an electrically erasable programmable read only memory (EEPROM) device, whose memory is erased by a sector-by sector bias. The state or data of a memory cell depends on the number of electrons stored in a gate structure of the cell. The cell's data is altered by applying a strong electric field between the gate structure and a source (or drain) to transfer electrons therebetween. The process of removing electrons from the gate structure is called an erase operation, and the process of accumulating electrons therein is called a program operation.
The flash memory device is classified into a stack gate or a split gate structure. The stack gate type flash memory is a most commonly used cell in flash memories and includes a control gate for receiving a driving voltage and a floating gate for storing electrons, wherein the control gate is simply stacked on the floating gate. The split gate type flash memory includes a select gate and a floating gate, wherein a portion of the select gate overlaps with the floating gate and the other portion thereof is arranged on a surface of a substrate.
FIG. 1 shows a cell array of a typical stack gate type flash memory device. The architecture includes a multiplicity of horizontal word lines “WL1-WLm” and a plurality of vertical bit lines “BL1-BLi”, “m” and “i” being integers, wherein a memory cell region is defined at each of the intersection regions of the word and the bit lines. Installed at each of the memory cell regions is a cell transistor “T” having a source “S”, a drain “D”, and a gate “G”. The source “S” of each transistor “T” is electrically connected to a common source line “SL”; the drain “D”, to a corresponding bit line; and the gate “G”, to a corresponding word line.
FIG. 2 presents a cross-sectional view of the cell transistor “T” shown in FIG. 1 according to a prior art. A source region 7a and a drain region 7b respectively serving as the source “S” and the drain “D” are disposed in a semiconductor substrate 2, on which a gate or tunnel oxide 3, a floating gate 4, an inter-gate insulating layer 5, and a control gate 6 are sequentially disposed. The drain region 7b is spaced apart from the source region 7a by a channel interposed therebetween. The floating gate 4 may overlap with opposing end portions of the source region 7a and the drain region 7b. 
In a typical program operation of the cell transistor “T” (FIG. 1), a first programming voltage (e.g., 10V) is applied to the control gate 6 via a corresponding word line and a second programming voltage (e.g., 6V) is applied to the drain region 7b via a corresponding bit line, while the source region 7a and the semiconductor substrate 2 are grounded. The first and the second programming voltage induce electrons at the channel region close to the drain region 7b to be injected through the gate oxide 3 into the floating gate 4 and stored therein, thus completing the program operation. In an erase operation, a first erasing voltage (e.g., 6V) is applied to the source region 7a via the source line “SL” (FIG. 1) and a second erasing voltage (e.g., −9V) is applied to a corresponding gate line, whereby the electrons stored in the floating gate 4 are removed to the source region 7a through the tunnel oxide 3.
Raising the erasing voltage or reducing the thickness of the tunnel oxide may provide a higher erase efficiency of the above-explained stack gate cell transistor. However, such an increased erasing voltage or a reduced thickness of the tunnel oxide deteriorates the durability of the flash memory device.